1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs EDI8L32128C august , 2002 rev. 6 white electronic designs corp. reserves the right to change products or speci?cations without notice. 128kx32 cmos high speed static ram ? 128kx32 bit cmos static ? random access memory array ? fast access times: 12, 15, 17, 20, and 25ns ? individual byte enables ? user con?gurable organization with minimal additional logic ? master output enable and write control ? ttl compatible inputs and outputs ? fully static, no clocks ? surface mount package ? 68 lead plcc, no. 99 (jedec mo-47ae) ? small footprint, 0.990 sq. in. ? multiple ground pins for maximum noise immunity ? single +5v (5%) supply operation the EDI8L32128C is a high speed, high performance, four megabit density static ram organized as a 128kx32 bit array. four chip enables, write control, and output enable provide the user with a ?exible memory solution. the user may independently enable each of the four bytes, and, with minimal additional peripheral logic, the unit may be con?gured as a 256kx16 or 512kx8 array. fully asynchronous circuitry is used, requiring no clocks or refreshing for operation and providing equal access and cycle times for ease of use. the EDI8L32128C, allows 4 megabits of memory to be placed in less than 0.990 square inches of board space; a savings of 0.885 square inches over four standard 128kx8 components. note: pin 2 & 67 on the 64kx32 (edi8l3265c) and the 256kx32 (edi8l32256c) are word select pins. block diagram fig. 1 pin configuration pin description a?-16 address inputs e?-3# chip enables (one per byte) w# master write enable g# master output enable dq?-31 common data input/output v cc power (+5v5%) v ss ground nc no connection top view dq0-dq7 dq8-dq15 dq16-dq23 dq24-dq31 128kx32 memory array a 0-a16 g# w# e0# e1# e2# e3# 17 dq17 dq18 dq19 v ss dq20 dq21 dq22 dq23 v cc dq24 dq25 dq26 dq27 v ss dq28 dq29 dq30 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 dq14 dq13 dq12 v ss dq1 1 dq10 dq9 dq8 vcc dq7 dq6 dq5 dq4 v ss dq3 dq2 dq1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 dq31 a6 a5 a4 a3 a2 a1 a0 v cc a13 a12 a1 1 a10 a9 a8 a7 dq0 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 dq16 nc nc e3# e2# e1# e0# nc v cc nc nc g# w# a16 a15 a14 dq15 features description note: solder re?ow temperature should not exceed 230c
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs EDI8L32128C august , 2002 rev. 6 white electronic designs corp. reserves the right to change products or speci?cations without notice. absolute maximum ratings* recommended dc operating conditions *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance ( f = 1.0mh z , v in = v cc or v ss ) ac test conditions dc electrical characteristics voltage on any pin relative to v ss -0.5v to 7.0v operating temperature t a (ambient) commercial industrial 0c to + 70c -40c to +85c storage temperature -55c to +125c power dissipation 4 watts output current. 20 ma junction temperature, t j 175c parameter sym min typ max units supply voltage v cc 4.75 5.0 5.25 v supply voltage v ss 0 0 0 v input high voltage v ih 2.2 -- v cc +0.5 v input low voltage v il -0.3 -- 0.8 v parameter sym max unit address lines c a 40 pf data lines c d/q 10 pf write & output enable lines w#, g# 40 pf chip enable lines/byte select e0-3# 8 pf truth table e# w# g# mode output power h x x standby high z i cc2 ,i cc3 l h h output disable high z i cc1 l x x output disable high z i cc1 l h l read d out i cc1 l l x write d in i cc1 parameter sym conditions typ max units 12* 15 17 20/25 operating power supply current i cc1 w# = v il , ii/o = 0ma, min cycle 620 720 680 640 600 ma standby (ttl) supply current i cc2 e# v ih , v in v il or v in v ih , f = ?mh z 160 160 160 160 ma full standby cmos supply current i cc3 e# v cc -0.2v v in v cc -0.2v or v in 0.2v 20 20 20 20 ma input leakage current i li v in = 0v to v cc 10 a output leakage current i lo v i/o = 0v to v cc 10 a output high volltage v oh i oh = -4.0ma 2.4 v output low voltage v ol i ol = 8.0ma 0.4 v input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 2 note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 3) typical: t a = 25c, v cc = 5.0v figure 2 figure 3 v cc q 480 ? 30 pf 255 ? v cc q 480 ? 5 pf 255 ?
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs EDI8L32128C august , 2002 rev. 6 white electronic designs corp. reserves the right to change products or speci?cations without notice. fig. 4 read cycle 1 - w# high, g#, e# low ac characteristics - read cycle parameter symbol 12ns 15ns 17ns 20ns 25n units jedec alt. min max min max min max min max min max read cycle time t avav t rc 12 15 17 20 25 ns address access time t avqv t aa 12 15 17 20 25 ns chip enable access time t elqv t acs 12 15 17 20 25 ns chip enable to output in low z (1) t elqx t clz 2 3 3 3 3 ns chip disable to output in high z (1) t ehqz t chz 7 8 8 10 10 ns output hold from address change t avqx t oh 3 3 3 3 3 ns output enable to output valid t glqv t oe 5 6 8 8 10 ns output enable to output in low z (1) t glqx t olz 2 2 2 2 0 ns output disable to output in high z(1) t ghqz t ohz 4 5 6 8 10 ns note 1: parameter guaranteed, but not tested. fig. 5 read cycle 2 - w# high a q t ava v address 1 t av qv t av qx d ata 1 address 2 d ata 2 a e# g# q t avav t av qv t elqv t elqx t glqv t glqx t ehqz t ghq z
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs EDI8L32128C august , 2002 rev. 6 white electronic designs corp. reserves the right to change products or speci?cations without notice. a g# e# w# d q t avav t av wh t el wh t wl wh t av wl t gla x t whax t dvwh t whdx t wlqz high z t whqx da ta v alid fig. 7 write cycle 2 - e# controlled fig. 6 write cycle 1 - w# controlled parameter symbol 12ns 15ns 17ns 20ns 25ns units jedec alt. min max min max min max min max min max write cycle time t avav t wc 12 15 17 20 25 ns chip enable to end of write t elwh t eleh t cw t cw 8 8 9 9 10 10 15 15 20 20 ns ns address setup time t avwl t avel t as t as 0 0 0 0 0 0 0 0 0 0 ns ns address valid to end of write t avwh t aveh t aw t aw 9 9 10 10 12 12 15 15 15 15 ns ns write pulse width t wlwh t wleh t wp t wp 9 9 10 10 12 12 15 15 15 15 ns ns write recovery time t whax t ehax t wr t wr 0 0 0 0 0 0 0 0 0 0 ns ns data hold time t whdx t ehdx t dh t dh 0 0 0 0 0 0 0 0 0 0 ns ns write to output in high z (1) t wlqz t whz 0 5 0 6 0 7 0 7 0 10 ns data to write time t dvwh t dveh t dw t dw 5 5 6 6 8 8 8 8 12 12 ns ns output active from end of write (1) t whqx t wlz 2 2 2 2 2 ns ac characteristics - write cycle note: parameter guaranteed, but not tested. a e# w# d q t avav t av eh t eleh t wleh t ehax high z da ta v alid t dve h t ehdx t av el
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs EDI8L32128C august , 2002 rev. 6 white electronic designs corp. reserves the right to change products or speci?cations without notice. part number speed (ns) package no. EDI8L32128C12ac 12 99 EDI8L32128C15ac 15 99 EDI8L32128C17ac 17 99 EDI8L32128C20ac 20 99 EDI8L32128C25ac 25 99 ordering information part number speed (ns) package no. EDI8L32128C15ai 15 99 EDI8L32128C17ai 17 99 EDI8L32128C20ai 20 99 0.995 ma x 0.956 ma x 0.995 ma x 0.956 ma x 0.040 ma x 0.020 0.015 0.930 0.890 0.050 bsc 0.1 15 ma x 0.180 ma x package description package no. 99: 68 lead plcc jedec mo-47ae all dimensions are in inches commercial (0 c to +70c) industrial (-40 c to +85c)
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